1. Field of the Invention
The present invention relates in general to floating-point arithmetic devices, and more particularly to a floating-point arithmetic device using a leading-zero anticipation circuit to increase an operation speed.
2. Description of the Prior Art
In a floating-point arithmetic device, generally, an input operand for calculation is composed of a sign block representing addition (xe2x80x9c+xe2x80x9d) or subtraction (xe2x80x9cxe2x88x92xe2x80x9d), an exponent block representing a magnitude of the operand and a significand block representing significant digits. For example, if the input operand is 0.11xc3x9728, the exponent is xe2x80x9c8xe2x80x9d and the significand is xe2x80x9c11xe2x80x9d.
In floating-point addition, exponents of two significands are compared with each other and one of the significands wish the smaller exponent is shifted to the right. Then, the two significands are summed and the number of consecutive leading zeros is calculated from the summed result. This procedure is performed on the assumption that a most significant bit of the significand is always 1 for the effective use of hardware in the expression of a real number, which is called normalization.
The significand after this procedure of normalization is expressed in a range between 0.5 and 1.0.
Such a conventional floating-point arithmetic device will hereinafter be mentioned with reference to the accompanying drawings.
FIG. 1 is a block diagram showing the construction of a conventional TFT-LCD floating-point arithmetic device and FIG. 2 is a detailed circuit diagram of a leading-zero anticipation circuit in FIG. 1.
With reference to FIG. 1, the floating-point arithmetic device comprises an input aligner 2 for suitably aligning two input operands, a controller 1 for comparing exponents of the input operands aligned by the input aligner 2 with each other and generating a control signal in accordance with the compared result, and a first multiplexer 3 for selecting a larger one of the exponents of the input operands in response to the control signal from the controller 1. A second multiplexer 4 selects a significand of one of the input operands with the larger exponent in response to the control signal from the controller 1 and a third multiplexer 5 selects a significand of the other input operand with a smaller one of the exponents in response to the control signal from the controller 1. An exponent difference calculator 6 is adapted to calculate a difference between the exponents of the input operands. A right shifter 7 shifts the significand selected by the third multiplexer 5 to the right by the exponent difference calculated by the exponent difference calculator 6 to establish digit matching. A significand comparator 8 acts to compare the significands selected by the second and third multiplexers 4 and 5 with each other. First and second bit inverters 9 and 10 invert the significand selected by the second multiplexer 4 and the significand shifted by the right shifter 7 in response to an output signal from the significand comparator 8, respectively, to take two""s complements thereof for subtraction by an adder 11 which will hereinafter be mentioned. The adder 11 is adapted to add output values from the first and second bit inverters 9 and 10. A leading-zero anticipation circuit 12 functions to anticipate the consecutiveness of leading zeros from the output values from the first and second bit inverters 9 and 10. A leading-zero counter 13 counts the number of the leading zeros anticipated by the leading-zero anticipation circuit 12. A rounding controller 14 is adapted to estimate a rounding condition to store an output value from the adder 11 in a specific bits number. As incrementer 17 adds xe2x80x9c1xe2x80x9d to a least significant bit of the stored value under the control of the rounding controller 14. A left shifter 15 acts to shift the output value from the adder 11 to the left by the number counted by the leading-zero counter 13. A selector 18 functions to select one of an output value from the left shifter 15 and an output value from the incrementer 17 under the control of the rounding controller 14 according to whether the right shifter 7 and second bit inverter 10 are in operation. A compensation shifter 19 shifts an output significand from the selector 18 to perform digit compensation when it is the maximum. An exponent subtracter 16 is adapted to subtract the number counted by the leading-zero counter 13 from the larger exponent selected by the first multiplexer 3. A sign controller 20 determines a sign of the final output value according to signs of the input operands. An exponent incrementer 22 acts to increment an output exponent from the exponent subtracter 16 to compensate for the leading-bit position. An output aligner 21 is adapted to align an output sign from the sign controller 20, an output exponent from the exponent incrementer 22 and an output significand from the compensation shifter 19 to provide the final output value.
The leading-zero anticipation circuit 12 has a construction as shown in FIG. 2.
In FIG. 2, the leading-zero anticipation circuit 12 is shown to calculate bit values at respective digits of the significands of the two input operands, on the assumption that the significands are each composed of m bits Am, Amxe2x88x921, . . . , Ai, Aixe2x88x921, . . . , A1, A0 and Bm, Bmxe2x88x921, . . . , Bi, Bixe2x88x921, . . . , B1, B0,. Namely, the leading-zero anticipation circuit 12 includes a NAND gate 23 for NANDing values of two input bits A, and B of the same digit, a NOR gate 24 for NORing the values of the two input bits Ai and Bi of the same digit, an inverter 25 for inverting an output value from the NOR gate 24, an OR gate 26 for ORing the inverted ones of output values from the inverter 25 and NAND gate 23, and a NAND gate 27 for NANDing the inverted one of the NORed result of values of two input bits Aixe2x88x921 and Bixe2x88x921 of the next digit and an output value from the OR gate 26.
Now, the operation of the conventional floating-point arithmetic device with the above-mentioned construction will be described.
First inputted over respective external data buses are two operands, each of which is composed of a sign block representing addition (xe2x80x9c+xe2x80x9d) or subtraction (xe2x80x9cxe2x88x92xe2x80x9d), an exponent block representing a magnitude of the operand and a significand block representing significant digits.
The input aligner 2 suitably aligns the two input operands and the controller 1 compares exponents of the input operands aligned by the input aligner 2 with each other and generates a control signal in accordance with the compared result so that a significand of one of the input operands with the smaller exponent can be outputted through the third multiplexer 5 and the larger exponent can be outputted through the first multiplexer 3.
As a result, in response to the control signal from the controller 1, the first multiplexer 3 selects the larger exponent, the third multiplexer 5 selects the significand of the input operand with the smaller exponent and the second multiplexer 4 selects a significand of the other input operand with the larger exponent.
The exponent difference calculator 6 calculates a difference between the exponents of the input operands and the right shifter 7 shifts the significand selected by the third multiplexer 5 to the right by the exponent difference calculated by the exponent difference calculator 6 to establish digit matching.
The significand comparator 8 compares the significands selected by the second and third multiplexers 4 and 5 with each other.
In order to provide two""s complements to input terminals of the adder 11 for subtraction, the first bit inverter 9 inverts the significand selected by the second multiplexer 4 in response to an output signal from the significand comparator 8 and the second bit inverter 10 inverts the significand shifted by the right shifter 7 in response to the output signal from the significand comparator 8. In the case of non-subtraction, the first and second bit inverters 9 and 10 pass their input values directly without inverting them.
The adder 11 adds output values from the first and second bit inverters 9 and 10. In the case of addition, the adder 11 performs the addition regardless of the magnitudes of two input values. But, in the case of subtraction, the adder 11 always subtracts the smaller value from the larger value, Accordingly, the added or subtracted result of the adder 11 is always positive.
The significand comparator 8 performs the comparison operation as follows:
if Axe2x89xa7B, then Axe2x80x2=A, Bxe2x80x2=/B
if A less than B, then Axe2x80x2=/A, Bxe2x80x2=Bxe2x80x83xe2x80x83[equation 1]
The adder 11 executes the calculation of xe2x80x9cAxe2x88x92Bxe2x80x9d as the operation of xe2x80x9cA+/B+1xe2x80x9d and the calculation of xe2x80x9cBxe2x88x92Axe2x80x9d as the operation of xe2x80x9cB+/A+1xe2x80x9d.
The leading-zero anticipation circuit 12 anticipates the consecutiveness of leading zeros from the output values from the first and second bit inverters 9 and 10 and the leading-zero counter 13 counts the number of the leading zeros anticipated by the leading-zero anticipation circuit 12.
That is, the leading-zero anticipation circuit 12 performs the following arithmetic operation for respective digits:
xe2x80x83Ei=/(Aixe2x80x2⊕Bixe2x80x2)xc2x7(Aixe2x88x921xe2x80x2+Bixe2x88x921xe2x80x2)=(Aixe2x80x2xc2x7Bixe2x80x2+/(Aixe2x80x2+Bixe2x80x2))xc2x7(Aixe2x88x921xe2x80x2+Bixe2x88x921xe2x80x2)xe2x80x83xe2x80x83[equation 2]
The leading-zero counter 13 counts the output Em, Emxe2x88x921, . . . , Ei, Eixe2x88x921, . . . , E1, E0 of the leading-zero anticipation circuit 12 so as to count the number of consecutive leading zeros. Namely, in the case where the output of the leading-zero anticipation circuit 12 is 000001011, the leading-zero counter 13 counts xe2x80x9c5xe2x80x9d.
On the other hand, a most significant bit of the output value from the adder 11 may be xe2x80x9c0xe2x80x9d. In order to make the most significant bit xe2x80x9c1xe2x80x9d, the left shifter 15 shifts the output value from the adder 11 to the left by the number counted by the leading-zero counter 13.
In order to store the output value from the adder 11 in a specific bits number, the rounding controller 14 estimates a rounding condition to output a round-up or down signal. The incrementer 17 adds xe2x80x9c1xe2x80x9d to a least significant bit of the stored value under the control of the rounding controller 14. The selector 18 selects one of an output value from the left shifter 15 and an output value from the incrementer 17 under the control of the rounding controller 14, resulting in the significand calculation being completed.
The exponent subtracter 16 subtracts the number counted by the leading-zero counter 13 from the larger exponent selected by the first multiplexer 3, resulting in the exponent calculation being completed.
However, in the above-mentioned conventional floating-point arithmetic device, the smaller significand is always subtracted from the larger significand, thereby causing the significand comparator and two bit inverters to be required. This requirement makes the circuit construction complicated and decreases the operation speed.
Therefore, the present invention has been made in view of the above problem, and it is an object of the present invention to provide a floating-point arithmetic device in which a leading-zero anticipation circuit is implemented to calculate input operands regardless of their magnitudes, so as to increase an operation speed.
In accordance with the present invention, the above and other objects can be accomplished by a provision of a floating-point arithmetic device comprising first control means for comparing signs of two input operands with each other and generating a control signal in accordance with the compared result; significand output means for calculating a difference between exponents of said input operands, outputting a significand of one of said input operands with a larger one of said exponents as it is, shifting a significand of the other input operand with a smaller one of said exponents by the calculated exponent difference and outputting the shifted significand; a multiplexer for selecting said larger exponent in response to said control signal from said first control means; a first bit inverter for inverting said significand with said larger exponent from said significand output means for subtraction in response to said control signal from said first control means; an adder for adding said shifted significand with said smaller exponent from said significand output means and an output value from said first bit inverter; leading-zero anticipation means for anticipating the consecutiveness of leading zeros from said significand with said larger exponent and said shifted significand with said smaller exponent from said significand output means; leading-zero counting means for counting the number of said leading zeros anticipated by said leading-zero anticipation means; second control means for estimating a rounding condition to store an output value from said adder in a specific bits number; a left shifter for shifting the output value from said adder to the left by said number counted by said leading-zero courting means; a second bit inverter for taking two""s complement of an output value from said left shifter if the output value from said adder is negative; an incrementer for incrementing an output value from said second bit inverter by one under the control of said second control means to provide a final significand; a compensation shifter for shifting the final significand from said incrementer to perform digit compensation when it is the maximum; an exponent subtracter for subtracting said number counted by said leading-zero counting means from said larger exponent selected by said multiplexer; and a decrementer for decrementing an output exponent from said exponent subtracter by one to provide a final exponent.